System Development Board DAT Series CM4MB Optional Product High -speed AD conversion board-HSAD500
System Development Board DAT Series CM4MB Optional Product High -speed AD conversion board-Prime Systems Co., Ltd.

System Development Board DAT Series CM4MB Optional Product High -speed AD conversion board
Prime Systems Co., Ltd.


About This Product

■ Characteristics ・ AD conversion option board for KX-CARD7 / AX-CARD7M / CM4MB. ・ You can select a signal path that can use the gain amplifier and a signal path that you do not use. ・ It can be changed to 800msps. ・ Customize the sample FPGA circuit to improve development efficiency. ・ You can use the design service to add and manufacture analog FAE circuits. The HSAD500 High-speed AD conversion board is an option board for KX-Card7 system development board. The 500MSPS 12-bitad converter IC and the KX-Card7 FPGA are composed of a 12ch parallel LVDS, configuring a high-performance system that secures signal integrity. In addition, a low jitter clock, which is indispensable for high -speed sampling, can configure high -precision AD conversion systems without impairing the performance provided by the AD converter IC. High -precision data after AD conversion can be various digital processing and USB data transfer, such as high -speed signal processing in FPGA, saving to DDR3 memory, and files by transferring high -speed data to PCs. ■ Functional 1ch 12bit 500msps (TI ADS5403) * It can also be changed to 800msps type ADS5401.

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    System Development Board DAT Series CM4MB Optional Product High -speed AD conversion board

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1 Models of System Development Board DAT Series CM4MB Optional Product High -speed AD conversion board

Product Image Part Number Price (excluding tax) Analog input connector Analog input specifications FPGA-IF General -purpose I/O connector others
System Development Board DAT Series CM4MB Optional Product High -speed AD conversion board-Part Number-HSAD500

HSAD500

$ 890.50〜 SMA connector single end/differential, AC/DC bond switching 1. Compatible with differential/single end input up to 1VPP 50Ω impedance
2. Implement an input path equipped with LPF (equipped with an amplifier circuit of max.26db, SPI control from FPGA)
Parallel DDR LVDS Convert 35 FPGA-IO pins into 2.54mm pitch 30 pin connectors
* If the gain amplifier is controlled by SPI from the FPGA, it will be 30).
Sampling frequency can be adjusted with clock synthesizer

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