Smart-USB SIGMA (USB3.0 compatible) System Development Board ZQ-CARD Options 16ch High-speed AD conversion board
Prime Systems Co., Ltd.
About This Product
■ Characteristics
･ Compatible with simultaneous sampling of up to 160ch with 10 units in parallel connection.
･ AD conversion option board for KX-CARD7 / AX-CARD7M / CM4MB.
･ Customize the sample FPGA circuit to improve development efficiency.
･ It is also possible to make an analog front -end circuit board using the design service.
The HSAD100D high-speed AD conversion board is an option board for KX-CARD7 and AX-Card7M system development board. The 100msps 12bit 16ch AD converter and FPGA are interfaced with LVDS2 lane/ch.
In addition, you can build a system that allows you to sample up to 160ch simultaneously by operating multiple boards. High -precision data after AD conversion can be various digital processing and USB data transfer, such as high -speed signal processing in FPGA, saving to DDR3 memory, and files by transferring high -speed data to PCs.
■ Functional
･ 16ch simultaneous sampling 12bit 100mSPS (adopted by TI ADS5295)
･ Up to 10 clock distribution functions. Compatible with simultaneous sampling of up to 160ch by parallel operation of multiple units.
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Product
Smart-USB SIGMA (USB3.0 compatible) System Development Board ZQ-CARD Options 16ch High-speed AD conversion board
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Handling Company
Prime Systems Co., Ltd.
1 Models of Smart-USB SIGMA (USB3.0 compatible) System Development Board ZQ-CARD Options 16ch High-speed AD conversion board
| Product Image | Part Number | Price (excluding tax) | Analog input connector | Analog input specifications | Board size | Clock distribution connector | FPGA-IF | General -purpose I/O connector | others |
|---|---|---|---|---|---|---|---|---|---|
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HSAD100D |
$ 1,452.00〜 | MMCX connector single end/differential, AC/DC binding switching | Compatible with differential/single end input Up to 2VPP 50Ω impedance input with built -in filter | 120 x 180 (mm) 8 layers domestic production PBFREE | 2.54 mm pitch 40 pinkonectors for clock distribution / timing synchronization 2 | LVDS (Serdes) 2 Lane/CH: 600Mbps per lane | Convert 48 FPGA-IO pins into 2 2.54mm pitch 34 pins connectors. 24ch configuration is possible as LVDS. | It also supports multiple units in parallel operation, and supports ultrasonic measurements such as 32ch, 64ch, 96ch, 128ch. |
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About Company Handling This Product
- Japan
- Since 1998
- 3 employees