Instantly visualize Verilog HDL/VHDL RTL source code HDL Auto SpecDraw
Strategy Co., Ltd.

About This Product

■Visualize project structure- Analyze and display the hierarchical structure by simply reading the source code files included in the project all at once.
- You can check the relationships between modules, signal connections, number and position of instantiated modules, etc.
- No need to trace signal connections from the RTL source code.
- Instantly analyze hierarchical structure.

■Visualize with just the source code- The analyzed source code can be displayed as a block diagram.
・You can now visually follow the signal connections, which greatly improves analysis efficiency compared to following the source code as text.
-Comments can be placed freely on the block diagram, making the document highly readable.
- RTL source code can be viewed as a block diagram, freeing you from complicated analysis work.

■Display the state machine in a diagram・The always clause (Verilog) /process clause (VHDL) that describes a state machine can automatically generate a state machine diagram (state transition diagram).
・You can easily follow the operation flow.
・Display the state machine in a diagram.
・Operation analysis is possible without reading the source code.

■Report analysis results in text-Analysis results can not only be expressed graphically, but also reported in text format.
- It is possible to report not only the hierarchical structure but also various information such as signal connections and the number of registers in the module.
・We support the creation of documents such as reports and specifications.
・It is possible to report a variety of information.
- Can also be used to manage new RTL source code during design.

Operating environment
■Windows 8/8.1・Processor: 800MHz 32bit (x86) /64bit (x64) (1GHz or higher recommended)
・Installed memory (RAM) capacity: 2GByte or more (4GByte or more recommended)

■Windows 10/11・Processor: 1GHz 32bit (x86) /64bit (x64) (1.2GHz or higher recommended)
・Installed memory (RAM) capacity: 2GByte or more (4GByte or more recommended)

■HDD free spacePlease ensure at least 50MByte.

■Peripheral equipmentA display and mouse with a resolution of SuperVGA (800 x 600) or higher.

Model
There is 1 model available for this product.

Product
Instantly visualize Verilog HDL/VHDL RTL source code HDL Auto SpecDraw

Handling Company
Strategy Co., Ltd.

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1 Models of Instantly visualize Verilog HDL/VHDL RTL source code HDL Auto SpecDraw

Image	Part Number	Price (excluding tax)	Parsable elements	Supported languages	Operating environment	Signal connection destination display function	Block diagram display function	State machine display function
	HDL Auto SpecDraw	$ 585.00〜	Hierarchical structure Number of registers used Number of input/output terminals Signal destination State machine diagram (state transition diagram)	Verilog HDL VHDL We can also handle mixed language projects.	Microsoft®Windows 8 / 8.1 / 10 / 11 (Japanese version / English version)	Copy connection diagram screenshot to clipboard in BMP format	No limit to the number or complexity of source code Copy the schematic screenshot to the clipboard in BMP format	Analyze always clause (Verilog) /process clause (VHDL) and display in state machine diagram Copy a screenshot of the state machine diagram to the clipboard in BMP format

Image

Part Number

Price (excluding tax)

Parsable elements

Supported languages

Operating environment

Signal connection destination display function

Block diagram display function

State machine display function

HDL Auto SpecDraw

$ 585.00〜

Hierarchical structure
Number of registers used
Number of input/output terminals
Signal destination
State machine diagram (state transition diagram)

Verilog HDL
VHDL
We can also handle mixed language projects.

Microsoft®Windows 8 / 8.1 / 10 / 11 (Japanese version / English version)

Copy connection diagram screenshot to clipboard in BMP format

No limit to the number or complexity of source code
Copy the schematic screenshot to the clipboard in BMP format

Analyze always clause (Verilog) /process clause (VHDL) and display in state machine diagram
Copy a screenshot of the state machine diagram to the clipboard in BMP format

About Company Handling This Product

Strategy Co., Ltd.

Japan

Instantly visualize Verilog HDL/VHDL RTL source code HDL Auto SpecDraw Strategy Co., Ltd.

About This Product

■Visualize project structure

■Visualize with just the source code

■Display the state machine in a diagram

■Report analysis results in text

■Windows 8/8.1

■Windows 10/11

■HDD free space

■Peripheral equipment

1 Models of Instantly visualize Verilog HDL/VHDL RTL source code HDL Auto SpecDraw

HDL Auto SpecDraw

About Company Handling This Product

Instantly visualize Verilog HDL/VHDL RTL source code HDL Auto SpecDraw
Strategy Co., Ltd.