About This Product
■ Product overview
・ Combine two functions that support ALDEC RTAX prototyping (two families (two RTAX-S/SL and RTSX-SU/S, SX-A) EDIF Netlist conversion and PDC/PIN constraints re-mapping. We provide).
・ From RTAX-S/SL and RTSX-SU/S, from SX-A EDIF Internet list to ProAsic3/EDIF Internet list, the difference between RTAX-S/SL and RTSX-SU/S, SX-A, PROASIC3/E Technology. Execute automatic conversion while considering the restrictions in (it means that PLL and memory primitives need to be replaced).
・ Automatic conversion of PDC (RTAX-S/SL) and PIN (RTSX-SU/S, SX-A) constraints is also executed, and from the pinlocation of RTAX-S/SL, RTSX-SU/S, SX-A. PROASIC3/E -pin Location enables automatic re -mapping according to the aldeck adapter board.
・ Supplement hardware adapters, enable seamless migration from RTAX-S/SL and RTSX-SU/S, SX-A, and use flash-based FPGA prototyping. Promote.
■ Benefit
・ Microchip SoC Proasic3/E-device ALDEC RTAX-S/SL, RTSX-SU/S, seamless prototyping with SX-A prototype boards.
・ Automatic conversion from RTAX-S/SL, RTSX-SU/S, SX-A net list to ProAsic3/e-Internet list. It is not necessary to execute the primitive and memory block manual mapping.
・ Automatic conversion of PDC and PIN restriction file. Providing an easy path to the P & R process along with the converted EDIF.
・ Additional library for memory for memory is available. The library can be used as an add -on option to the basic configuration.
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Product
Emulation RTAX/RTSX Netto List Converter