About This Product

■ Hybrid verification platform ・ Fully automatic ・ This is a hybrid verification environment for scalable SOC/ASIC design. ・ Use the latest coordination emulation standards such as SCE-MI and TLM and the latest FPGA technology to prepare the design hardware prototypes early. ・ You can develop and verify high -abstract code with RTL accuracy and high -speed SOC emulation and models with high speed -up functions, resulting in reduced test time and silicon / rispin risk. ■ Many solutions on 1 platform ・ Various applied bells and SOC/ASIC design verification can be performed. ・ Many applications that use TLM rapper and high -speed AXI/AHB buses and transuctors can connect designs mounted in hardware with virtual platforms. -Exes a powerful debug tool that can visualize the inside of the module running with FPGA, and the HES-DVM emulation platform is as easy to use as an RTL simulator. ■ Scalability and reuse 1. Scalability is the basic concept of the backbone of the HES-DVM ™ project, and is the source of our solution's uniqueness. 2. Main characteristics ・ Supported FPGA board -Adec's HES prototyping board -Custom boards made by other companies or in -house development ・ Verification interface ・ Automatic design setup ・ Debugging function ■ Physical prototyping 1. Supports design split, clock conversion, and mapping to FPGA, and to make chip connection designs using serialization methods to overcome the FPGA I/O restrictions. 2. Main characteristics ・ Supported FPGA board -Adec's HES prototyping board -Custom boards made by other companies or in -house development ・ Automatic design set up ・ Scalability and reuse

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    Emulation HES-DVM

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4 Models of Emulation HES-DVM

Items marked with have different values depending on the model number.

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Product Image Part Number Price (excluding tax)

DVM-PROTO

Available upon quote

DVM-XL

Available upon quote

DVM-EMU

Available upon quote

DVM-ELITE

Available upon quote

Click on the part number for more information about each product

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