Semiconductor ASIC Embedded Array
Seiko Epson Corporation
About This Product
■Embedded array
Embedded arrays are semi-custom ICs that are equipped with hard macros for specific applications such as standard cells and ASSPs, and can be implemented and integrated with customer's circuits using Sea of Gate. A system-on-chip is possible by converting highly integrated, high-performance cells into hard macros, and by converting the logic section into a Sea of Gate system, the development period after the wiring process is the same as that of a gate array.
Additionally, the LSI base (base bulk) can be reused, and changes can be made in the same development period as gate arrays if only the logic part is changed.
■Embedded array design method
The design method for an embedded array is to first design the system, determine the number of gates in the logic section and the macro cells to be installed, and then begin manufacturing the base bulk.
The base bulk is equipped with the necessary hard macro cells and is also covered with Sea of Gate for the logic section, and manufacturing proceeds up to the wiring stage. In parallel with this manufacturing work, we carry out work from logic section circuit design to post-layout simulation fixes, just as with normal gate arrays, and after sign-off, we carry out the wiring process. After sign-off, samples will be shipped with the same delivery time as gate arrays. Additionally, the base bulk of the LSI can be reused, so if you only need to change the circuit of the logic section, it can be done with the same development cost and development lead time as a gate array.
Embedded arrays are semi-custom ICs that are equipped with hard macros for specific applications such as standard cell macros and ASSPs as functional blocks, and configure customer circuits with Sea of Gate. While incorporating the same functions as standard cells, the logic section is made into a sea of gates, allowing for a development period comparable to that of gate arrays. Additionally, since it is relatively easy to change the circuit, it can be used to avoid the risk of product modification.
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Product
Semiconductor ASIC Embedded Array
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Handling Company
Seiko Epson Corporation
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Categories
4 Models of Semiconductor ASIC Embedded Array
Items marked with have different values depending on the model number.
Click on the part number for more information about each product
| Product Image | Part Number | Price (excluding tax) | Features | Macrocell | Package | Series name | Status |
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S1X80000 |
Available upon quote | Highly integrated (0.15μm CMOS 4/5 layer wiring process adopted, 74K gates/mm2), high-speed operation (internal gate delay: 34.5ps/1.8V, 2-input NAND Typ.), etc. | Can be equipped with RAM, PLL, LVDS, RSDS, and various macro cells | QFP48~256 pins, PBGA, PFBGA, QFN | S1X80000 series | MP |
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S1X60000 |
Available upon quote | High integration (0.25μm CMOS 3/4/5 layer wiring process adopted, number of installed gates: up to 2.5 million gates), high-speed operation (internal gate delay: 107ps/2.5V, 2-input Power NAND Typ.), etc. | RAM, ROM, Flash, MCU, PLL, LVDS, RSDS, various macro cells can be installed | QFP48~256 pins, PBGA, PFBGA, QFN | S1X60000 series | MP |
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S1X50000 |
Available upon quote | Highly integrated (0.35μm CMOS 3/4 layer wiring process adopted), high-speed operation (internal gate delay: 150ps/3.3V, 2-input Power NAND Typ.), etc. | Can be equipped with RAM, ROM, Flash, MCU, PLL, analog cells, LVDS, RSDS, and various macro cells. | QFP48~256 pins, PBGA, PFBGA, QFN, WCSP | S1X50000 series | MP |
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S1X5V000 |
Available upon quote | High integration (0.35μm CMOS 2/3/4 layer wiring process adopted), high speed operation (internal gate delay: 0.19ns/5.0V, 0.29ns/3.3V, 2-input Power NAND Typ.), etc. | Can be equipped with RAM, ROM, Flash, MCU, PLL, analog cells, LVDS, RSDS, and various macro cells. | QFP48~256 pins, PBGA, PFBGA, QFN, WCSP | S1X5V000 series | MP |
Click on the part number for more information about each product
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About Company Handling This Product
- Japan