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History
Response Rate
100.0%
Response Time
29.3hours
Relatively Fast Response
Product
Semiconductor ASIC gate arrayHandling Company
Seiko Epson CorporationCategories
Click on the part number for more information about each product
| Image | Part Number | Price (excluding tax) | Delay time Output buffer | Delay time internal gate | Delay time Input buffer | Features | Output mode | Input mode | Status | Series name | I/O level |
|---|---|---|---|---|---|---|---|---|---|---|---|
|
|
S1L60000 |
Available upon quote |
Tpd=1,600ps (at 2.5V, CL=15pF) |
Tpd=107ps (at 2.5V, F/O=1, standard wiring load) |
Tpd=270ps (at 2.5V, F/O=2, standard wiring load) |
Ultra-high integration (0.25µm CMOS 3-layer/4-layer wiring process adopted), high-speed operation (internal gate delay 107ps at 2.5V 2-input NAND Typ.), etc. |
Normal, open-drain, 3-state, bidirectional, level shifter, fail-safe, gated |
CMOS, LVTTL, pullup/pulldown, Schmitt, level shifter, fail-safe, gated |
MP |
S1L60000 series |
CMOS, LVTTL, PCI-3.3V |
|
|
S1L50000 |
Available upon quote |
Tpd=2.12ns (at 5.0V) Level shifter, 2.02ns (at 3.3V), 3.9ns (at 2.0V), CL=15pF |
Tpd=0.14ns (at 3.3V, F/O=2, standard wiring load), 0.21ns (at 2.0V, F/O=2, standard wiring load) |
Tpd=0.38ns (at 5.0V, F/O=2, standard wiring load) Level shifter, 0.4ns (at 3.3V, F/O=2, standard wiring load), 1.3ns (at 2.0V, F/O= 2, standard wiring load) |
Highly integrated (0.35µm CMOS 2-layer/3-layer/4-layer wiring process adopted), high-speed operation (internal gate delay 0.14ns at 3.3V 2-input Power-NAND Typ.), etc. |
Normal, open-drain, 3-state, bidirectional, fail-safe, gated |
LVTTL, CMOS, pullup/pulldown, Schmitt, Fail-safe, Gated |
MP |
S1L50000 series |
CMOS, LVTTL, PCI-5V, PCI-3.3V |
|
|
S1L5V000 |
Available upon quote |
Tpd=2.07ns (at 5.0V), tpd=2.95ns (at 3.3V), CL=15pF |
Tpd=0.19ns (at 5.0V, F/O=2, standard wiring load), tpd=0.29ns (at 3.3V, F/O=2, standard wiring load) |
Tpd=0.45ns (at 5.0V, F/O=2, standard wiring load), tpd=0.55ns (at 3.3V, F/O=2, standard wiring load) |
Highly integrated (0.35µm CMOS 2-layer/3-layer/4-layer wiring process adopted), high-speed operation (internal gate delay: 0.19ns at 5.0V, 0.29ns at 3.3V, 2-input Power-NAND Typ.), etc. |
Normal, open-drain, 3-state, bidirectional, fail-safe, gated |
TTL, LVTTL, CMOS, pull-up/pull-down, Schmitt, Fail-safe, Gated |
MP |
S1L5V000 series |
CMOS, TTL, LVTTL |
Click on the part number for more information about each product
Reviews shown here are reviews of companies.
Reviews shown here are reviews of companies.
Response Rate
100.0%
Response Time
29.3hrs
