Semiconductor ASIC gate array
Seiko Epson Corporation
About This Product
■Gate array
Epson's gate arrays allow you to freely set the power supply and signal arrangement, making them ideal for replacing existing products. In 2012, in response to customer requests, we newly developed the S1L5V000 series, which uses a 0.35um process and supports a 5V single power supply, contributing to improved integration and power consumption.
Gate arrays are constructed by preparing a base bulk in which transistors (basic cells) are arranged in regular arrays (columns) in advance, and then constructing an LSI using only the wiring process. It is generally characterized by a short development period. In addition, it is possible to select the base bulk according to the number of gates and terminals.
■ASIC product lineup
Epson ASIC has a lineup of gate arrays, embedded arrays, and standard cells. By adopting these series, we will provide optimal solutions to our customers.
・Extensive support history since 1982
・Integrated operation with in-house design and related factory production
・ISO9001, IATF16949 certification
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Product
Semiconductor ASIC gate array
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Handling Company
Seiko Epson Corporation
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Categories
3 Models of Semiconductor ASIC gate array
Items marked with have different values depending on the model number.
Click on the part number for more information about each product
| Product Image | Part Number | Price (excluding tax) | Delay time Input buffer | Delay time Output buffer | Delay time internal gate | Features | I/O level | Input mode | Output mode | Series name | Status |
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S1L60000 |
Available upon quote | Tpd=270ps (at 2.5V, F/O=2, standard wiring load) | Tpd=1,600ps (at 2.5V, CL=15pF) | Tpd=107ps (at 2.5V, F/O=1, standard wiring load) | Ultra-high integration (0.25µm CMOS 3-layer/4-layer wiring process adopted), high-speed operation (internal gate delay 107ps at 2.5V 2-input NAND Typ.), etc. | CMOS, LVTTL, PCI-3.3V | CMOS, LVTTL, pullup/pulldown, Schmitt, level shifter, fail-safe, gated | Normal, open-drain, 3-state, bidirectional, level shifter, fail-safe, gated | S1L60000 series | MP |
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S1L50000 |
Available upon quote | Tpd=0.38ns (at 5.0V, F/O=2, standard wiring load) Level shifter, 0.4ns (at 3.3V, F/O=2, standard wiring load), 1.3ns (at 2.0V, F/O= 2, standard wiring load) | Tpd=2.12ns (at 5.0V) Level shifter, 2.02ns (at 3.3V), 3.9ns (at 2.0V), CL=15pF | Tpd=0.14ns (at 3.3V, F/O=2, standard wiring load), 0.21ns (at 2.0V, F/O=2, standard wiring load) | Highly integrated (0.35µm CMOS 2-layer/3-layer/4-layer wiring process adopted), high-speed operation (internal gate delay 0.14ns at 3.3V 2-input Power-NAND Typ.), etc. | CMOS, LVTTL, PCI-5V, PCI-3.3V | LVTTL, CMOS, pullup/pulldown, Schmitt, Fail-safe, Gated | Normal, open-drain, 3-state, bidirectional, fail-safe, gated | S1L50000 series | MP |
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S1L5V000 |
Available upon quote | Tpd=0.45ns (at 5.0V, F/O=2, standard wiring load), tpd=0.55ns (at 3.3V, F/O=2, standard wiring load) | Tpd=2.07ns (at 5.0V), tpd=2.95ns (at 3.3V), CL=15pF | Tpd=0.19ns (at 5.0V, F/O=2, standard wiring load), tpd=0.29ns (at 3.3V, F/O=2, standard wiring load) | Highly integrated (0.35µm CMOS 2-layer/3-layer/4-layer wiring process adopted), high-speed operation (internal gate delay: 0.19ns at 5.0V, 0.29ns at 3.3V, 2-input Power-NAND Typ.), etc. | CMOS, TTL, LVTTL | TTL, LVTTL, CMOS, pull-up/pull-down, Schmitt, Fail-safe, Gated | Normal, open-drain, 3-state, bidirectional, fail-safe, gated | S1L5V000 series | MP |
Click on the part number for more information about each product
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About Company Handling This Product
- Japan