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History
Price (excluding tax)
Response Rate
100.0%
Response Time
72.2hours
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Delay time Input buffer
Delay time Output buffer
Delay time internal gate
Features
I/O level
Input mode
Output mode
Series name
Status
Part Number
S1L50000Product
Semiconductor ASIC gate arrayHandling Company
Seiko Epson CorporationCategories
| Image | Price (excluding tax) | Delay time Input buffer | Delay time Output buffer | Delay time internal gate | Features | I/O level | Input mode | Output mode | Series name | Status |
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Available upon quote | Tpd=0.38ns (at 5.0V, F/O=2, standard wiring load) Level shifter, 0.4ns (at 3.3V, F/O=2, standard wiring load), 1.3ns (at 2.0V, F/O= 2, standard wiring load) | Tpd=2.12ns (at 5.0V) Level shifter, 2.02ns (at 3.3V), 3.9ns (at 2.0V), CL=15pF | Tpd=0.14ns (at 3.3V, F/O=2, standard wiring load), 0.21ns (at 2.0V, F/O=2, standard wiring load) | Highly integrated (0.35µm CMOS 2-layer/3-layer/4-layer wiring process adopted), high-speed operation (internal gate delay 0.14ns at 3.3V 2-input Power-NAND Typ.), etc. | CMOS, LVTTL, PCI-5V, PCI-3.3V | LVTTL, CMOS, pullup/pulldown, Schmitt, Fail-safe, Gated | Normal, open-drain, 3-state, bidirectional, fail-safe, gated | S1L50000 series | MP |
Reviews shown here are reviews of companies.
Reviews shown here are reviews of companies.
Response Rate
100.0%
Response Time
72.2hrs
