TSOI Wafer
Icemos Technology Japan Co., Ltd.
About This Product
We provide dielectric isolation technology, such as separating high voltage parts and components on a single chip. Isolation consists of thick SOI and high aspect ratio deep trench etch and oxide and poly fill structures. Applicable to 100-150mm wafer size, device layer thickness 1.5-100um.
■Optional supply
・Supply of dielectric isolation substrate using isolation mask
・Providing dielectric isolation ICs that have undergone isolation process in advance using Icemos as a foundry
・Full IC design supply and manufacturing with dielectric separation from customer's circuit
■Later isolation technology can be applied
・Simple Bipolar
・CMOS (1P,2M)
・BiCMOS (1P,2M)
■Trench isolation SOI substrate has the advantage of completely separating the dielectric material into each tab.
・Eliminating the embedded layer
・Eliminating epi layer
・Eliminating P+ isolation
・Minimize parasitic capacitors
・High quality crystalline silicon layer
・Increase die yield per wafer at the same time
・High voltage resistance capability
・Customized trench pattern
Our process engineers work closely with your design group to bring process development to fruition.
■Application
・MEMS devices
・Solid state relay photoelectric generator
・Photovoltaic cells and optoelectronic device ICs
・High voltage analog IC for telecommunications
・High performance bipolar circuit
・Smart power IC
・Integrated sensor
■Main features
・Complete device isolation
- Significantly promotes die size reduction compared to conventional junction isolation method
・Lower defect density compared to conventional DI technology
・Substrate capacitance lower than bulk
・Cost lower than trench isolation using EPI
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Product
TSOI Wafer
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Handling Company
Icemos Technology Japan Co., Ltd.
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Categories
3 Models of TSOI Wafer
Items marked with have different values depending on the model number.
Click on the part number for more information about each product
| Product Image | Part Number | Price (excluding tax) | Buried oxide film Thermal oxide film Buried oxide film | Device Thickness Tolerance Range | Device layer Buried layer implant | Device layer Final field oxide film | Device layer Silicon growth method | Device layer Trench filling-oxide film (both sides) | Device layer Trench filling-polysilicon | Device layer crystal orientation | Device layer dopant type | Device layer doping | Device layer low efficiency | Device layer planarization | Device layer thickness | Device layer trench aspect ratio | Device layer trench lateral diffusion doping | Device layer trench line width | Device layer trench mask tone | Device layer trench mask type | Handle layer back side treatment | Handle layer crystal orientation | Handle layer dopant type | Handle layer doping | Handle layer layer thickness range | Handle layer resistivity | Handle layer silicon growth method | Handle thickness | Handle thickness tolerance range |
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TSOI Wafer Wafer diameter 100mm |
Available upon quote | 0.2-4.0μm by handle, device or both wafers | ±0.5 μm | N type or P type | Thermal oxide film + TEOS up to 1μm | CZ, MCZ or FZ | 0.1-1.0μm | To full (doped or undoped polysilicon) | 100, 111 or 110 | N or P | N type: Phos, Red Phos, Sb＆As P type: Boron | ≤0.001 - ≥10,000 Ω-cm | CMP | ≥1.5-100μm | 15:1 | Phosphorus | >2μm | Positive resistance | E-beam master for projection aligner | By lapping, etching or polishing | 100, 111 or 110 | N or P | N type: Phos, Red Phos, Sb＆As P type: Boron | 350-1,150μm | ≤0.001 - ≥10,000 Ω-cm | CZ, MCZ or FZ | 350-800μm | ±5μm |
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TSOI Wafer Wafer diameter 125mm |
Available upon quote | 0.2-4.0μm by handle, device or both wafers | ±0.5 μm | N type or P type | Thermal oxide film + TEOS up to 1μm | CZ, MCZ or FZ | 0.1-1.0μm | To full (doped or undoped polysilicon) | 100, 111 or 110 | N or P | N type: Phos, Red Phos, Sb＆As P type: Boron | ≤0.001 - ≥10,000 Ω-cm | CMP | ≥1.5-100μm | 15:1 | Phosphorus | >2μm | Positive resistance | E-beam master for projection aligner | By lapping, etching or polishing | 100, 111 or 110 | N or P | N type: Phos, Red Phos, Sb＆As P type: Boron | 350-1,150μm | ≤0.001 - ≥10,000 Ω-cm | CZ, MCZ or FZ | 350-800μm | ±5μm |
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TSOI Wafer Wafer diameter 150mm |
Available upon quote | 0.2-4.0μm by handle, device or both wafers | ±0.5 μm | N type or P type | Thermal oxide film + TEOS up to 1μm | CZ, MCZ or FZ | 0.1-1.0μm | To full (doped or undoped polysilicon) | 100, 111 or 110 | N or P | N type: Phos, Red Phos, Sb＆As P type: Boron | ≤0.001 - ≥10,000 Ω-cm | CMP | ≥1.5-100μm | 15:1 | Phosphorus | >2μm | Positive resistance | E-beam master for projection aligner | By lapping, etching or polishing | 100, 111 or 110 | N or P | N type: Phos, Red Phos, Sb＆As P type: Boron | 350-1,150μm | ≤0.001 - ≥10,000 Ω-cm | CZ, MCZ or FZ | 350-800μm | ±5μm |
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