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  2. Functional Verifation ALINT-PRO (Aldec Japan Co., Ltd.)
Functional Verifation ALINT-PRO-ALINT-PRO
Functional Verifation ALINT-PRO-Aldec Japan Co., Ltd.

Functional Verifation ALINT-PRO
Aldec Japan Co., Ltd.

About This Product

■ Product overview

・ Coding style and naming rules, simulation disagreement between RTL and synthesis results, smooth and optimal synthesis, correct FSM description, after design, clock and reset tree problems, CDC, RDC, DFT, and portability and portability. This is a verification solution that analyzes the RTL code described in VHDL, Verilog, and SystemVerilog, focusing on coding for use. ・ Static analysis is performed based on RTL and SDC ™ source files, finding serious design problems at an early stage of design, contributing to greatly reducing the design time.

■ Main functions

・ Analysis of clock reset / network ・ Prevent mismatches for RTL simulation and simulation after synthesis ・ Verification of accuracy of FSM description ・ Graphical analysis of detected FSM and identified FSM problem ・ Code portability and reuse ・ A wide range of CDC and RDC checks by Aldec_CDC rule plug -in ・ Advanced CDC and RDC debugging environment ・ Skematic viewer, etc.

■ A single framework for DRC and CDC/RDC analysis

・ We provide functions for efficient design analysis with intuitive frameworks designed appropriately. ・ We support a very simple GUI wizard that can be imported directly in a setup to analyze existing HDL design. ・ Full chip level -level lin -tin -tinning

■ Check of FPGA design

・ Smoothly support the rule check of the design targeting the implementation of FPGA with the minimum setting. ・ We provide the latest version of FPGA vendor library. ・ Auto the IP -based FPGA design hierarchy and setup of incremental analysis flow.

■ Batch mode flow

・ Design rules can be checked, settings, and report generation can be automated. ・ Ideal for integration with large regression test script and continuous integration environment.

■ Rule libraries available in ALINT-PRO ™

Includes rule libraries based on Starc and RMM Design Guidelines, which utilize the best practices of design development used by semiconductor companies around the world.

  • Product

    Functional Verifation ALINT-PRO

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1 Models of Functional Verifation ALINT-PRO

Image Part Number Price (excluding tax)
Functional Verifation ALINT-PRO-Part Number-ALINT-PRO

ALINT-PRO

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About Company Handling This Product

Aldec Japan Co., Ltd.

  • Japan

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