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  2. MIPI DPHY-Tx (Silicon Library Co., Ltd.)
MIPI DPHY-Tx-DPHY-Tx
MIPI DPHY-Tx-Silicon Library Co., Ltd.

MIPI DPHY-Tx
Silicon Library Co., Ltd.

About This Product

■Summary

The MIPI D-PHY analog TX IP core complies with D-PHY specification version 1.2 and supports MIPI-CSI-2 and DSI protocols. This Tx-PHY has one clock lane and four data lanes, consists of an analog front end and a digital section to control the I/O, and includes a termination resistor with automatic calibration.

■Features

・Compliant with MIPI D-PHY specification version 1.2 ・Supports MIPI standard PPI interface ・Supports high-speed mode transfer with data rate 80-2500 Mbps ・Supports low power mode transfer with data rate 10Mbps ・Supports ultra-low power mode, high speed mode, and escape mode ・Supports 1 clock lane and up to 4 data lanes -Data lane supports data transfer in high-speed mode. - Supports error detection mechanisms for sequence errors and conflicts ・Supports conflict detection errors - Skew adjustment possible for each clock and data lane

  • Product

    MIPI DPHY-Tx

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1 Models of MIPI DPHY-Tx

Image Part Number Price (excluding tax)
MIPI DPHY-Tx-Part Number-DPHY-Tx

DPHY-Tx

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About Company Handling This Product

Silicon Library Co., Ltd.

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