USB2.0 PHY
Silicon Library Co., Ltd.

About This Product

■SummaryUSB2.0 PHY IP is a physical layer (PHY) IP solution designed for high performance and low power consumption. This IP implements a high-speed USB 2.0 transceiver and can be used for hosts and devices.

The USB2.0 PHY IP integrates mixed-signal circuitry that complies with the UTMI+ Level 3 specification to support high-speed data rates of 480Mbps and is backward compatible with full-speed (12Mbps) and low-speed (1.5Mbps) data rates. Auxiliary USB battery charging specifications are also supported for mobile and consumer product applications.

■Features- Fully compliant with USB 2.0 specifications
・Supports UTMI+ level 3 specifications
・Supports USB battery charging
Supports 480 Mbps High Speed ​​(HS), 12 Mbps Full Speed ​​(FS), and 1.5 Mbps Low Speed ​​(LS) data transmission speeds
・Can be configured as a host controller or device peripheral
・Use 8-bit@60Mhz or 16-bit@30Mhz interface
・Supports USB 2.0 test mode
・Built-in high speed, full speed, and low speed test functions
・High-speed serial clock can be generated from data clock using on-chip PLL
・Input reference clock frequency (12/24/25MHz) selectable
・1 port or 2 port configuration possible