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■ Overview / features The IPC600 is a kit for evaluation of IPC9XXX, IPC17XX and IPC1603 of CHIP ON FPGA. IPC9XXX, IPC17XX and IPC1603 use the IEEE 1588v2 -compliant boundary, master and slave clock that is optimized by the highest level of technology to provide high -quality frequency synchronization and time (TOD) on the packet network. 。 The IPC9XXX, IPC17XX and IPC1603 are implemented as CHIP ON FPGA in XILINX's Spartan6 FPGA, using 8MB flash memory and 64MB DDR II memory. The IPC600 has an RS232 TOD interface via a 100/1,000 Mbps Ethernet connection via CLK IN, CLK OUT, PPS, and RJ45 via the BNC connector, via the DB9 connector. The IPC600 can be monitored by the user via the RS232 management port. The IPC600 also displays the following status by several LEDs. System power, device status (pass, alarm, fleet), clock state (freelancer, holdover, trace/lock). ■ Provided 1. IPC600 body (using IPC500 board) 2. Accessories 3. Documents ・ IPC600 EVB Datasheet ・ IPC600 User Manual ・ IPC600 Schematics ・ IPC600 SCHEMATICS -Application Note The following documents can be provided by the Mutual NDA conclusion. ・ IPC9xxx_17xx_1603 User Guide ・ IPC9000 Datasheet
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IPC600Handling Company
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