Optimized for high-speed networking and high-speed, large-capacity memory access, FPGA board S7T-VG6
Fuji Soft Co., Ltd.
About This Product
■ Overview / Features
Bittware with GDDR6 and QSFP-DD Achronix Speedster7T FPGA board
The S7T-VG6 offers a 7nm Achronix FPGA optimized for high-speed networking and high-speed large memory access. The board with a QSFP-DD (Double-Density) cage supports up to 1x 400GBE or 4X 100GBE using a 56G PAM4 SPEEDSTER®7T device. Additional QSFP ports support 2x 100GBE, and 4X MCIO connectors support NVME connection storage. The GDDR6 Graphic DRAM 16 channels process high -bandwidth memory requirements and provide up to 512GB/s.
The FPGA provides a large -scale logic and memory liberation with a 692k 692k lookuped table (LUT) and a built -in RAM of 189 MB. It also provides 2,560 MLP (Machine-Learning Blocks).
■ Specifications
1. QSFP cage
・ QSFP-DD cage of front panel
・ 56GPAM4 Transiver
・ 1x400GBE, 2x200GBE, 4x100GBE or 8x10/25/40/50GBE
・ Hard Mac and FEC
・ QSFP56 cage of front panel
・ 56GPAM4 Transiver
・ 1x200GBE, 2x100GBE, or 4x10/25/40/50GBE
・ Hard Mac and FEC
2. Board Management Controller
・ Voltage, current, temperature monitoring
・ Power sequence and reset
・ Field upgrade
・ FPGA configuration and control
・ Clock configuration
・ I2C bus access
・ USB2.0
・ Voltage override
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Product
Optimized for high-speed networking and high-speed, large-capacity memory access, FPGA board S7T-VG6
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Handling Company
Fuji Soft Co., Ltd.
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Categories
1 Models of Optimized for high-speed networking and high-speed, large-capacity memory access, FPGA board S7T-VG6
| Product Image | Part Number | Price (excluding tax) | External clocking | Foam factor | Fpga | GPIO | Host interface | Mcio | On -board flash | USB | cooling | electricity | environment |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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S7T-VG6 |
Available upon quote | 1PPS and 10MHZREFCLK front panel input | Standard-Height PCIE Dual-Width Board | Achronix Speedster AC7T1500: 52.5 X52.5 Package, 692K 6-Input Lookup Tables (Luts), etc. | Eight GPIO pins, 3.3V, single end, direction (TX, RX) can be set individually by FPGA for each GPIO, rated 200Mbps buffer. | PCIegen4 X16 interface directly connected to FPGA | Rear edge MCIO, PCIEGEN4 hard IP connected to FPGA via a 4X transceiver | 1 Bank with ECC DDR4-2666, up to 4 GBYTES (X72), Flash Memory Host interface for launching FPGA | USB port for accessing BMC, USB-JTAG, USB-UART, the second USB port for Daisy chain | Standard: Dual-Width Passive Heatsink, Other options | Onboard power supply from two AUX connectors (8 pins) | Operation temperature: 5 to 35 ℃ |
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About Company Handling This Product
- Japan