■ Overview / features
The H.264/AVC HD encoder IP core is a real -time encoder of HD video or video/audio data. The single core can encode a resolution of up to 1,920 x 1,080 with 60fps, up to 120 fps. The 30fps and 60fps latencies are 0.25ms and 0.125ms, respectively, to achieve ultra -low delay between input and output.
The core is optimized only for the use of very small footprints and ultra -low -powered FPGA resources. The efficiency of IP core is ideal for low -power -oriented electronic devices and devices that require large -scale processing.
As a feature, it is possible to provide two versions other than the standard version. Intra only and interfram slim version can be provided as an IP cores. Intra only is a 1/3 of the FPGA logic compared to the standard version, in exchange for about twice the size of the standard bit rate.
The interfram slim version is up to 1/2 FPGA logic size, which is used for a system that matches the low -end device or is extremely compressed with logic resources.
The slim version fits the application in a high network band that can accept high bit rate. This output bit rate is about 20%larger than the standard version.
■ Compatible devices, corresponding OS
Fpgas: Intel and Xilinx
■ Logic resource
1. intel
・ ALMS: 60,000
・ Block RAMS: 5,000kbits
・ DSPS: 310
・ EXAMPLE FPGA: CYCLONE V 5cea9
2. XILINX
・ LUTS: 90,000 (45,300 for slim version)
・ Block RAMS: 7,000 kbits
・ DSPS: 318 (71 for Slim Version)
・ EXAMPLE FPGAS: Spartan-6, Artix-7 A200T
* Audio will be provided for ARM CPU or for DSP (BK512).
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