IPC500 | Providing evaluation kit for the IPC series FPGA board
Fuji Soft Co., Ltd.
Price (excluding tax)
Model Description
■ Overview / features The IPC500 is a kit for evaluation of IPC9XXX, IPC17XX and IPC1603 of CHIP ON FPGA. The IPC9XXX, IPC17XX and IPC1603 use high -quality frequency synchronization and time (TOD) to provide high -quality frequency synchronization and time (TOD) on the packet network using IEEE 1588V2 compliant boundaries, masters and slab clocks. I am. The IPC9XXX, IPC17XX and IPC1603 are implemented as CHIP ON FPGA in XILINX's Spartan6 FPGA, using 8MB flash memory and 64MB DDR II memory. The IPC500 has an RS232 TOD interface via a 100/1,000 Mbps Ethernet connection via CLK IN, CLK OUT, PPS, and RJ45 via the BNC connector, via the DB9 connector. The IPC500 can be monitored by the user via the RS232 management port. The IPC500 also displays the following status by several LEDs. System power, device status (pass, alarm, fleet), clock state (freelancer, holdover, trace/lock). ■ Provided 1. IPC500 board 2. Accessories 3. Documents ・ IPC500 EVB Datasheet ・ IPC500 User Manual ・ IPC500 Schematics ・ IPC500 SCHEMATICS -Application Note The following documents can be provided by the Mutual NDA conclusion. ・ IPC9xxx_17xx_1603 User Guide ・ IPC9000 Datasheet
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Part Number
IPC500
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Handling Company
Fuji Soft Co., Ltd.
Providing evaluation kit for the IPC series FPGA board IPC500's performance table
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About Company Handling This Product
- Japan
- Since 1970
- 9,570 employees